Solid state and so-called flash memories are known in the art. An individual flash memory cell includes a metal-oxide-semiconductor ("MOS") device having spaced-apart drain and source regions fabricated on a substrate and defining a channel region therebetween. A very thin gate oxide layer overlies the channel region, and a floating charge-retaining storage gate overlies the channel region and is unconnected to the cell. A control gate at least partially overlies the floating gate and is insulated therefrom.
In practice, a plurality of such memory cells is arrayed in addressable rows and columns to form a flash memory array. Individual cells in the array are accessed for purposes of writing, reading or erasing data by decoding row and column information.
Typically, the control gates for a group of cells in a given row are formed from a continuous strip of conductive material that defines a so-called word line, abbreviated "WL". A word line might comprise, for example, a group of eight cells that collectively store one byte. For a given column in the array, the drain leads of all cells in the column are coupled to a so-called bit line, abbreviated "BL". The source leads of the various cells are collectively switchably coupled to one of several potential levels, depending upon whether cells in the array are to be programmed (written) or erased or are to be read.
Within the memory array, an individual cell is addressed and thus selected for reading, programming (writing) or erasing by specifying its row (or word line) as an x-axis coordinate, and its column (or bit line) as a y-axis coordinate. A 16 K-bit memory, for example, may comprise an array of 128.times.128 bits, in which there are 128 x-axis word lines and 128 y-axis bit lines. Commonly, blocks of memory cells are collectively grouped into sectors. Cell addressing is accomplished by coupling address bits to precoding x-decoders and to precoding y-decoders whose respective outputs are coupled to word lines and bit lines in the array.
Programming an addressed MOS memory cell occurs in a program mode by accelerating so-called hot electrons (from the device substrate). These electrons are injected from the drain region through the thin gate oxide and onto the floating gate. The control gate-source threshold voltage required before substantial MOS device drain-source current occurs is affected by the amount of such charge retained on the floating gate. Thus, storage cell programming forces the floating storage gate to retain charge that will cause the cell to indicate storage of either a logical "1" or "0" in a read-out mode.
The above-described storage cells are non-volatile in that the charge on the storage gate, and thus the "0" or "1" bit stored in the cell, remains even when control and operating voltages to the array are turned off. In the program (write) mode, the control gate is coupled to a high positive potential of perhaps +10 VDC, the drain is coupled to perhaps +6 VDC, and the source and substrate are grounded (meaning that they are coupled to the circuit ground node). This causes the hot electrons to be generated and captured by the floating gate.
In a read mode, the charge stored on the floating gate of an addressed MOS memory cell is read by coupling perhaps +5 VDC to the control gate, and reading drain-to-source current. The presence or absence of charge on the stored gate will define a binary "1" or "0" bit that is read-out from the addressed memory cell by a sense amplifier coupled to the bit line.
In an erase mode, the electrons trapped on the floating gates of a group of addressed MOS memory cells are encouraged to flow by electron tunneling to the source. During this erase mode, a group of word line decoders cause the addressed cells' control gates to be coupled to ground, or 0 VDC, the sources to be coupled to perhaps +11 VDC and the drains to float, with the substrates being coupled to ground. Note that in a flash memory configuration, entire sector-sized blocks of cells may be simultaneously erased, in a "flash".
In the various read, program or erase modes, the word lines (e.g., control gates) are set to the appropriate voltage levels by x-decoder circuitry. One portion of such circuitry, a positive-voltage word line decoder, pulls selected word lines up to VCC during normal read mode and to the larger positive potential (e.g., +10 VDC) during programming mode, and grounds unselected word line sectors.
As mentioned above, when a memory cell is being erased, its control gate is tied to 0 VDC, its drain floats and its source is tied to a large positive voltage. The 0 VDC control gate voltage and large positive source voltage encourage the charge accumulated on the gate to flow into the source as a source current. If this source current is excessive, band to band tunneling could result, causing snap back and other adverse effects. If the source current is inadequate, the cell will not be completely erased. Consequently it is vital that, during an erase operation, the source current (and the source voltage, which causes the source current to flow) be maintained at the appropriate levels.
Prior art flash memory systems do not provide circuitry for reliably controlling flash cell source voltage or current during erase operations. Instead, the large positive source voltage is generated from an external, high voltage power supply (hereinafter called VPPESD), which can be highly variable (e.g., VPPESD can vary between 11.4 and 12.6 VDC). Due to the variability in VPPESD, during erase operations the large positive source voltage and source current are likely to vary and cause at least some of the adverse effects mentioned above. Moreover, because prior art memories lack current control circuitry, even if VPPESD happens to remain stable at the correct level for the duration of an erase operation, excessive power supply current could interfere with the programming of memory cells which are not to be erased.
Consequently, there is a need for on-chip control for controlling source current and voltage when a flash memory is being erased. In accordance with the present invention, this control circuitry could make use of stable reference voltage, such as a band-gap reference voltage, and a feedback control system to set the source voltage at the correct level. There is also a need for on-chip circuitry that ensures that the source voltage power supply does not provide excessive current that might interfere with cell programming.